Conventional DRAMs provide a random access to the memory circuit by storing each bit of data in a separate memory cell. Each memory cell includes a capacitor connected to an access transistor. The capacitor holds a charge representative of a data bit while the transistor accesses the capacitor during the reading and writing operations. A DRAM circuit includes an array of individual memory cells arranged in rows and columns. Each row of memory cells communicates with a word line and each column of memory cells communicates with one of a bit line or a complimentary bit line. Data is transmitted to and from each memory cell through the bit line and the complementary bit line.
The data is typically accessed through the cell address which identifies a memory cell by its row and column in the array. To address a memory cell in the array, the memory circuit identifies the memory cell located at an intersection between the identified row and column. To read or write (store) information to a memory cell, it must first be selected or addressed. Addressing a memory cell is accomplished by inputting signals to a row detector and a column detector. The row detector activates a word line responsive to the row address, and the selected word line in turn activates the access transistors for all memory cells in communication with the word line. Similarly, the column decoder identifies a pair of bit line and complementary bit line in response to the column address. Thus, when reading a cell, the selected word line activates the access transistor for a row address and data is latched to the bit line and the complementary bit line in communication with the desired cell.
As stated, the capacitor in a memory cell stores a charge which represents the logical state of the memory. A logical state of 1 represents a charge stored on the capacitor and a discharged capacitor has a logical state of 0. The bit line and the complementary bit line communicate the charge of the capacitor to a sense amplifier which senses small charge differentials on the bit line pair. The sense amplifier also connects the bit line pairs to power supply rails for reading the memory cell or writing onto the cell.
Conventional sense amplifiers use a back-to-back inverter by cross-coupling a pair of pull down transistors and a pair of pull-up transistors. Among others, the back-to-back inverter drives the appropriate charge to the bit line pair in order to conduct the refreshing and the writing operations. If the memory cell contains a charge different from the charge that is to be written, the inverter will oppose or fight the sensing operation, thereby delaying the writing operation and consuming additional power.